A frequently used fabrication technique in the manufacture of semiconductor devices involves the deposition of a metallic layer on the surface of a wafer. The deposition process utilizes a thin metal coating to cover steps such as in vias or contact holes that have diameters in the submicron range. The process is essential for achieving precise pattern alignment and reliability in fabricating VLSI (very large scale integration) and ULSI (ultra-large scale integration) devices.
Typically, a wafer surface is etched at a plurality of locations which produces a stepped configuration of spaced lines, trenches, vias and contact holes, i.e., the wafer surface is far from being planar. A key requirement of a deposition process is to uniformly and completely fill the trenches and holes to achieve a generally planar surface. However, the task to completely fill the holes and trenches by using conventional deposition techniques without void formation is very difficult. The presence of voids in a via or contact formed results in poor quality and defective IC devices.
A conventional sputter apparatus that is used to fill trenches or contact holes arranged in a cluster form is shown in FIG. 1. The cluster tool 10 consists of four physical vapor deposition chambers 12, 14, 16 and 18 arranged surrounding a transfer chamber 20. On the other end of the cluster tool 10, a number of auxiliary chambers 22, 24, 26 and 28 are arranged surrounding a buffer chamber 30. Further surrounding and in fluid communication with the buffer chamber 30 are the load lock chambers 36 and 38. The buffer chamber 30 and the transfer chamber 20 are both equipped with a wafer transfer robot 32 which is equipped with a robot blade 34. The cluster tool 10 is mounted in a wafer fabrication facility by through-the-wall installation such that the load lock chambers 36, 38 face the clean room and the process chambers 12˜18 are located in a service area. The load lock chambers 36, 38 are used for load and unload wafers into and out of the cluster tool by a machine operator.
Inbetween the buffer chamber 30 and the transfer chamber 20 are positioned two intermediary chambers, i.e., a pre-clean chamber 40 and a cool-down chamber 42. The pre-clean chamber 40 is used for pre-cleaning a wafer before it is delivered to the transfer chamber and subsequently into a sputter chamber. The cool-down chamber 42 is utilized for cooling down a substrate between a high temperature sputter process and a low temperature sputter process.
A detailed, perspective view of the cool-down chamber 42 is shown in FIG. 2. The cool-down chamber 42 may be constructed by a wafer pedestal 44, a chamber base 46, a wafer lifting device 48, a chamber housing 50 which includes a wafer port 52 and a pumping port 54, a wafer lifting ring 58 and a chamber cover 60. As shown in FIG. 2, the wafer lifting device 48 operates through the chamber base 46 on the wafer lifting ring 58 for loading and unloading of a wafer (not shown) onto and off the top surface 62 of the wafer pedestal 44. The wafer is first delivered through the wafer port 52 into the chamber housing 50 by a robot blade. The wafer pedestal 44 is cooled by internal cooling channels (not shown) in which a cooling water is circulated through during the operation of the cool-down chamber 42. When a wafer is positioned on the top surface 62 of the wafer pedestal 44, the bottom surface of the wafer is cooled by heat conductance between the wafer and the wafer pedestal 44 while the top surface of the wafer is cooled by a cooling gas circulated through a cavity in the chamber housing 50. The cooling gas circulated through the cavity is normally an inert gas such as argon, nitrogen or helium.
In the cluster tool 10 shown in FIG. 1, a semiconductor substrate is frequently processed in several sputter chambers during a multi-layer deposition process. For instance, a frequently used sputtering process involves the deposition of an aluminum/copper alloy on a substrate surface followed by the deposition of an anti-reflective coating (ARC) layer on top by a material such as TiN so that the metal layer can be processed in a subsequent photolithographic process. The ARC coating layer is important since it avoids a focusing problem that otherwise result from a reflective surface of the aluminum.
In a typical AlCu/TiN process, the processing temperatures used for the two sputtering processes vary to a large extent. For instance, the AlCu deposition may be conducted at a temperature of about 300° C., while the TiN sputtering process may be conducted at a temperature below 200° C. A rapid cool-down process must therefore be conducted to reduce the temperature of the substrate between the two processes. In the operation of the cool-down chamber 42, it has been noticed that the cooling of the bottom side of a substrate is inefficient using a conventional pedestal even though an intimate contact is established between a smooth wafer surface and a smooth pedestal surface. The cooling efficiency by heat conductance to the cooling fluid flown through the wafer pedestal does not approach that of the cooling fluid flown through the chamber cavity for cooling the top surface of the wafer. Due to a significant difference existed between the cooling rates on the top surface and on the bottom surface of the wafer, thermal stresses produced by the temperature difference are also significantly different in the top surface and in the bottom surface of the wafer. Since wafers are very thin, a large difference in the thermal stresses existed between the two surfaces frequently cause a vertical movement of the wafer from the pedestal surface, i.e., the wafer jumps up from the pedestal surface to at least 1 cm. Whenever the wafer jump occurs, the position of the wafer is changed on the pedestal and thus the loading of the wafer by the wafer lifting ring 58 is dislocated. This results in an inaccurate placement of the wafer or more seriously, the dropping of the wafer from the lifting ring resulting in a total loss of the wafer.
Furthermore, the intimate contact between two smooth surfaces of the wafer and the wafer pedestal frequently results in a suction force between the two surfaces. The suction force prevents the wafer from being picked up by the wafer lifting ring 58 and thus cause further processing difficulties.
It is therefore an object of the present invention to provide a wafer pedestal for cooling a semiconductor substrate positioned thereon that does not have the drawbacks or shortcomings of the conventional wafer pedestals.
It is another object of the present invention to provide a cooling stage for a semiconductor substrate that can be effectively used as a wafer pedestal for improved cooling of a semiconductor substrate.
It is a further object of the present invention to provide a cooling stage for a semiconductor substrate that can be used effectively in cooling a semiconductor substrate without the occurrence of the wafer jump phenomenon.
It is another further object of the present invention to provide a cooling stage for a semiconductor substrate that can be used efficiently for cooling a substrate without creating a suction force between the substrate and the cooling stage.
It is still another object of the present invention to provide a cooling stage for a semiconductor substrate that utilizes a wafer pedestal provided with a grooved surface for achieving improved cooling of the wafer.
It is yet another object of the present invention to provide a cooling stage for a semiconductor substrate wherein a pedestal is equipped with a plurality of circular grooves concentrically formed in a top surface and a plurality of linear grooves formed in radial directions emanating from a center of the top surface.
It is still another further object of the present invention to provide a method for cooling a semiconductor substrate by first providing a cooling stage that includes a wafer pedestal equipped with a grooved top surface, then flowing a cooling gas through the grooves to carry away heat from a backside of a semiconductor substrate positioned on the stage.
It is yet another further object of the present invention to provide a wafer pedestal that is effective in cooling a high temperature processed wafer that includes a pedestal that has a grooved surface including at least five circular grooves concentrically formed in the top surface and three linear grooves formed in radial directions emanating from a center of the top surface.